This invention relates to a total sum calculation circuit which is capable of calculating a total sum of a plurality of input data, each of which is represented by a floating point representation.
In general, it often happens that a conventional total sum calculation circuit of the type described is used in summing up three or more input data represented by a floating point representation to provide a total sum of the three or more input data. In this event, such input data may be referred to without loss of generality as first through n-th input data, where n is an integer greater than two. On calculating the total sum of the first through the n-th input data, the conventional total sum calculation circuit at first sums up two of the input data to calculate a first intermediate sum, as will be described in detail with reference to one of several drawing figures of the accompanying drawing. Thereafter, another of the input data and the first intermediate sum are summed up by the conventional total sum calculation circuit to calculate a second intermediate sum. Similar operations are successively carried out (n-1) times as regards the respective input data to calculate the total sum of the first through the n-th input data. Therefore, it takes a long time to carry out such successive summations of the first through the n-th input data.